The present invention relates to an information processing system, such as a personal computer (PC), and in particular to an information processing system with a power saving function that, as needed, reduces the operating frequency of a processor (a so-called CPU or Central Processing Unit), or entirely halts the operation of the processor in order to reduce the power consumption. More specifically, the present invention pertains to an information processing system that satisfies both requests for power saving and for security of a system, and that can reduce the operating frequency of the CPU or can entirely halt the operation of the CPU even during a period in which asynchronous communication with a peripheral device is executed.
As progress in the current technique continues, various types of personal computers (hereafter referred to as "PCs" or "systems"), such as desktop and notebook computers, are being manufactured and widely sold. The notebook PCs that are compact and light, since for their design, portability and outdoor use are taken into consideration.
One of the features of notebook PCs is that they are "battery operable" and can be driven by an incorporated battery. Such a system can be used at sites where there are no commercially available power sources. A battery that is incorporated in a notebook PC is commonly formed as a "battery pack", which is a package that comprises a plurality of rechargeable battery cells (also called a "secondary cell"), such as Ni-Cd, NiMH, or Li-Ion. Although such a battery pack is reusable by being recharged, the battery duration is sufficient to supply power for only two to three hours of system operation time. Therefore, various ideas for power saving have been implemented to extend the time between charge periods for a battery. The introduction of the power saving function can constitute another feature for the notebook PCs.
At present, from an ecological point of view, the demand for power saving has increased even for desktop PCs that can be powered almost endlessly by commercially available power sources. And in June 1993, the U.S. Environmental Protection Agency (EPA) advocated the self-imposed regulations called the "Energy Star Computer program", and required that power consumed in the standby state be lower than a predetermined value (driving power is to be 30 W or less, or 30% or less than it is when the CPU is active). Computer makers have developed and manufactured products that conform to the suggested regulation. For example, desktop PCs that have a power saving function are already sold by IBM Japan, Ltd. (e.g., the PS/55E (for which "Green PC" is a common name), PC 750, and the Aptiva series ("Aptiva" is a trademark of IBM Corp.)).
Power saving with a PC can be accomplished by, for example, reducing operational power consumption by the individual electric circuits in a system. Power savings can also be provided by reducing or halting, as needed, the power supply to the individual electric circuits (or peripheral devices) in the system in accordance with the reduction of their operational state (activity). The latter power saving function may especially be called a "power management" function.
The power management modes of a PC are an "LCD backlight-OFF" mode and an "HDD-OFF" mode, which halts the power supply to devices, such as an LCD (Liquid Crystal Display) and its backlight, or a rotary motor of an HDD (hard disk drive), that account for the greatest share of the total power consumption by a full system. The other example power management modes are a "CPU slow clock/stop clock" mode, in which the operating frequency of a CPU (Central Processing Unit) is reduced or the operation of the CPU is halted, and a "Suspend" mode, in which the power supply to all the electric circuits, except for a main memory, is halted after data required for resuming the task are saved in the main memory.
As is well known, CPU chips are the units that constitute the nuclei for the computations that are performed by computer systems. Recently, as production techniques for manufacturing semiconductor devices have improved, as is demonstrated by the reduction in the wiring width, the operating frequencies of CPUs have increased even more. For example, there have appeared CPU chips, such as the "Pentium" sold by Intel Corp. and the "PowerPC" (a trademark of IBM Corp. PowerPC is jointly developed by IBM Corp., Motorola Corp. and Apple Corp.), that can be driven at operating frequencies that exceed 100 MHz. The performance of a CPU and its operating frequency are very closely related. And as the operational speed of a CPU rises, the speed at which it performs calculations increases accordingly. A fast CPU demonstrates its excellent capabilities especially when running large application programs and when performing graphics procedures.
But as nothing is perfect, the high processing speed of the CPU brings with it several problems. One of the problems concerns the increased power consumption by the CPUs and the consequent heat generation. As the strength of a current that flows across a transistor gate (i.e., a resistor) per unit time increases, the power consumption and the heat generation also increase. Theoretically, the power consumption by a CPU is proportional to the operating frequency. Currently, the ratio of the power consumption by a CPU to the total power consumption by the system can not be ignored.
The power management functions of a CPU, such as the "CPU slow clock/stop clock", are provided to overcome the above described condition. The "slow clock" and the "stop clock" are modes in which, when the system determines that the CPU is in the standby state (i.e., the CPU is in the idle state: e.g., the condition that a predetermined time has elapsed since a last key/mouse input), power consumption is reduced by lowering the operating frequency of the CPU (i.e., the performance of the CPU is lowered), or by entirely halting its operating clock. It should be noted that the performance of the CPU is lowered only up to the point at which neither turn-around time (i.e., the time that elapses from the reception of a request until the generation of an affirmative response) nor through-put (the quantity of jobs per unit time) is deteriorated. The "slow clock" function and the "stop clock" function of the CPU will now be described.
The slow clock function of the CPU can be achieved by changing the frequency of a clock signal that is inputted by an external oscillator. This function can also be achieved by changing a CPU chip's internal operating frequency while maintaining a constant external input clock frequency. A high speed processing CPU ordinarily receives a relatively low clock signal (for example, 66 MHz) and internally increases the speed of an operating clock (to, for example, doubles the speed, 133 MHz) by using an incorporated PLL (Phase Lock Loop) circuit. It is difficult for this type of CPU to drastically change an input clock frequency to the CPU chip because of the characteristic of a PLL circuit (e.g., the inherent vibration count of the oscillator or a delay time (several msec) required until the phase locking is performed). Therefore, another design method is employed for a CPU chip that incorporates both a PLL circuit and a slow clock function (power management function) that internally switches an operating clock. According to this method, the incorporated PLL circuit usually increases an input clock speed while the internal slow clock function autonomously lowers the performance of the CPU in the chip.
FIG. 7 is a schematic diagram illustrating the internal arrangement of a CPU that incorporates a power management function. In FIG. 7, a CPU chip 11 comprises a functional unit 11a that actually performs computation; a PLL circuit 11b that transmits, to the functional unit 11a, an operating clock signal for synchronous driving; and a performance controller 11c that controls the performance of the functional unit 11a. The CPU chip 11 communicates with its peripheral devices (not shown) via a processor bus 12.
The function of a PLL circuit whereby the frequency of an input clock signal is multiplied is well known. The PLL circuit 11b doubles the speed (66 MHz, for example) of a relatively slow clock signal to obtain an operating frequency (133 MHz, for example), and transmits the doubled clock signal to the functional unit 11a.
The functional unit 11a can be divided into a computation unit (a double shaded portion in FIG. 7) and an internal cache/control unit. The computation unit is a section whose performance can, to a degree, be reduced in accordance with the activity of the system (it should be noted that the performance of the computation unit must be lowered only to the degree that the turn around time and the through-put are not deteriorated). The internal cache/control unit is a section that must respond to an external event, such as a cache snoop, an interrupt request (INTR/NMI/SMI), or a hold request (HOLD) of the bus 12, that occurs in a time critical manner and unperiodically, and thus, its performance can not be easily reduced regardless of the activity of the system.
The performance controller 11c controls the performance of the functional unit 11a in response to a control signal STPCLK# received from an external device. More specifically, while the STPCLK# is active (i.e., low), the controller 11c halts the supply of the operating frequency to the computation unit (the double shaded portion in FIG. 7) in the functional unit 11a. That is, the CPU chip 11 is so designed that its performance can be reduced locally. As a modification method, the STPCLK# inputted to the performance controller 11c is intermittently changed to active (i.e., goes low) to reduce the frequency of the operating clock transmitted from the PLL controller 11b. For example, if the STPCLK# is set active (i.e., goes low) according to a predetermined cycle and the frequency of the operating clock is reduced by one of n times, the performance and power consumption of the computation unit is reduced to about (n-1)/n. The function that intermittently affects the STPCLK# input operation is generally called "clock throttling" or "frequency emulation".
SL enhanced 486s, DX2s and DX4s, and Pentiums, which are chips that have succeeded the "80486" CPU chip from Intel Corp., have the power saving function that is shown in FIG. 7. These chips include STPCLK# as one of control signals along the processor bus 12.
The "stop clock" function completely suspends the input clocks supplied by the oscillator 40, and halts the entire functional unit 11a. The complete stopping of the operating clock can be accomplished by virtue of a fully static arrangement of the CPU chip 11 in which a storing and saving function is not required. In the "stop clock" mode, the power consumption by the CPU is, at most, several hundreds of mW. The stop clock function can be regarded as an ultimate power management operation.